1. Field of the Invention
The present invention relates to a high speed memory device which can read out data at a high speed. More particularly it relates to a high speed semiconductor memory and a high speed associative memory both having a cache memory.
2. Description of the Related Art
Various techniques have been developed to attain a high speed semiconductor memory. Examples of such techniques include the following:
(1) A high speed access technique using page mode addressing: PA1 (2) A technique utilizing a cache memory:
In sense amplifiers each having a latch for storing data, when the sensing operation of the sense amplifiers is finished, for example, n bits of data in the same row addresses are stored in the n sense amplifiers. Then any of the n bits of data can be rapidly selected and output by designating the column address.
According to this page mode technique, a series of storing operations are conducted by first latching the row address internally, and then changing the column address. The first row address is latched in response to the detection of the fall of an RAS signal. In this technique, data is read out by designating a column address through a column line corresponding to the column address, and then another piece of data is read out by designating another column address through another column line corresponding to the column address. During these operations, the row address is fixed.
According to the page mode addressing technique, in a DRAM with the size of, for example, 1024.times.1K bits (1M bits) having a cycle time of 155 nanoseconds (ns) in the normal mode, when input addresses are in the same row, 1024 of column addresses can be randomly accessed in a cycle time of 50 ns.
According to a technique utilizing a cache memory, tags and data are previously stored in a cache memory, and an input address is first compared with the tags in the cache memory. When the input address matches a tag, i.e., when the data corresponding to the input address is found in the cache memory, the data is output from the cache memory. As a result, a high speed data reading is attained.
As a high speed semiconductor memory adopting an improved technique utilizing a cache memory, an RDRAM developed by Rambus, U.S.A., is well known. The RDRAM comprises a slave (RDRAM) portion and a Rambus channel portion. The RDRAM uses the sense amplifier of a DRAM as a cache memory.
In this RDRAM, the size of a page which can be used as a cache memory in a DRAM of, for example, 4M bits is 8K bits. In other words, the RDRAM has a cache memory with two pages per one chip. This is four times as large as the capacity of a sense amplifier used in an ordinary DRAM with four M bits in the page mode. The Rambus channel portion connects the master portion with the RDRAM portion, and nine bits of signals are transferred at a rate of 500M-bytes/second, which is approximately ten times as high speed as in an ordinary DRAM.
In addition to the above-mentioned RDRAM, a synchronous DRAM and a cache DRAM have been reported as a high speed memory.
An associative memory is used to rapidly retrieve data matching a retrieval key word from the data stored in the data storage area. Such an associative memory addresses data depending upon the memory contents, simultaneously distributes the retrieval key word to the data storage areas, compares the key word and the data in parallel using the retrieval key word and a mask, and makes detection and search as a result of collation. Such an associative memory is described in, for example, "Content Addressable and Associate Memory", IEEE Computer, 1989 July, pp. 51-64.
As a conventional architecture for attaining an associative memory, a bit serial system, a byte serial system, a word serial system and a distributed logical memory are known. In the bit serial system, data is registered and retrieved in the storage area bit by bit. In the byte serial system, data is registered and retrieved in the storage area byte by byte. In the word serial system, the size of a logic portion can be smaller than in the distributed logical memory, resulting in a high density of the memory. The bit serial system, the byte serial system and the word serial system are preferred in a large scaled associative memory.
FIG. 15 is a schematic diagram of a conventional associative memory. The associative memory comprises a storage area 801 for storing M data Word.sub.1 through Word.sub.M to be retrieved. A retrieval key word is stored in a key word register 802. A mask pattern is stored in a mask register 803.
A plurality of data stored in the storage area 801 are collated with the retrieval key word in a collator 804 connected to the storage area 801 and the mask register 803. The collator 804 is connected to a collation flag register 805 with M bits. Collation flags are written in the collation flag register 805 as a result of the collation. The collation flag register 805 is connected to a flag detection circuit 806 for detecting the collation flags. The associative memory further comprises a retrieval circuit 807 connected to the storage area 801 and an output register 808 connected to the retrieval circuit 807.
The associative memory performs the associative retrieval in the bit serial system as follows: A retrieval key word and a mask pattern are first input to the collator 804 from the key word register 802 and the mask register 803, respectively. Data to be retrieved are input to the storage area 801 and the collator 804. The data to be retrieved herein are M data (Word.sub.1 through Word.sub.M), and each of the M data is input in parallel to the collator 804 bit by bit.
The collator 804 has M collation circuits respectively corresponding to the respective data. The retrieval key word and the data to be retrieved are input to each collation circuit bit by bit. The collation circuit is designed to output 1 when all the collated bits match and to output 0 when any of the collated bits mismatch. The output of each collation circuit corresponds to each bit of the collation flag register 805. Therefore, a bit in the collation flag register 805 corresponding to the word matching the retrieval key word alone is flagged. To each bit of the collation flag register 805, a register address corresponding to each word of the data is applied.
The collation flag detection circuit 806 outputs a register address signal when all the bits of the collation flag register 805 have a value of 1. The retrieval circuit 807 receives the collated register address, read outs the content in the address in the storage area 801, and outputs the content to the output register 808. The collation in the bit serial system is described in the above, but the collation in the byte serial system and the word serial system can be performed in a similar manner.
The above-mentioned conventional high speed semiconductor memory has the following problems:
In the page mode technique, the access rate is significantly decreased when the input addresses are not in the same row.
In the technique utilizing a cache memory, when the same input address is input a plurality of times, the second and later access can read out data at a high speed. With regard to the first access, however, the data sometimes does not exist in the high speed accessible latch or in the RAM. In such a case, the memory cell array is accessed again, resulting in an operation rate of 1/3 to 1/5 as low as the rate in the later access. In order to avoid this, i.e., in order to improve the cache hit ratio, it is necessary to enlarge the memory capacity of the cache memory, resulting in increasing the cost of the semiconductor memory.
Further, when the conventional technique utilizing a cache memory is used to attain a high speed associative memory, the operation rate is limited for the above-mentioned reasons.